The present invention relates generally to the fabrication of integrated circuits and, more particularly, to a method of removing an inorganic antireflective coating used in photolithography from a semiconductor substrate and to a method of forming features of an integrated circuit.
The trend in integrated circuit (IC) technology toward smaller feature sizes is approaching the use of features which are 0.25 .mu.m and smaller. To photolithographically pattern such small features, the use of an antireflective coating (ARC) becomes necessary. This ARC helps in the definition of small images by reducing the light scattering from the substrate into the photoresist. The introduction of an ARC, however, may have several detrimental consequences. For example, an inorganic bottom antireflective coating (BARC), e.g., SiON, cannot be easily removed unless additional wet or dry etch processes are added to the IC process flow. These additional etch processes may lead to excessive oxide loss at the oxide spacer of a transistor or in the field isolation. In the event the BARC layer undergoes high temperature thermal cycles or oxidation, it becomes even more difficult to etch and, consequently, the degree of oxide loss becomes more severe.
One of the key elements of deep submicron technology is a salicide process in which a self-aligned polycide gate structure is formed. The polycide gate structure includes a layer of refractory metal silicide on the top surface of the polysilicon gate. To obtain uniform metal silicide, the top surface of the polysilicon gate must be clean. When an inorganic BARC layer is used in photolithography, it is likely that the etch processes required to obtain a sufficiently clean polysilicon surface will result in excessive oxide loss at the oxide spacer or in the field isolation, as mentioned above. Thus, the use of an inorganic BARC layer may be incompatible with current IC process flows.
In view of the foregoing, there is a need for a method which facilitates easy removal of an inorganic BARC layer from a semiconductor substrate. Such a method would allow an inorganic BARC layer to be incorporated into the process flow for an IC, thereby enabling the patterning of small features, e.g., 0.25 .mu.m and smaller, without causing significant damage to neighboring areas of the IC.